Computer Systems and Engineering Seminar Series

Power Supply Impedance Emulation for LSI Testing

Speaker:Naoki Terao
Date: Friday, February 3, 2017
Time: 12:00pm - 1:00pm
Location: 208 Hudson Hall, Duke
Lunch will be served.

Abstract

In semiconductor test, mismatch of power supply integrity between an automatic test equipment (ATE) and a customer board can lead to test failures. This talk will discuss a technique to control the power supply impedance of an ATE by feedback control using compensation current injection so that it emulates the impedance of a customer board, so as not to produce test failures coming from the impedance difference between the two environment. Our technique adjusts the equivalent impedance by injecting compensation current by a current source attached in parallel with the power supply source. The compensation current is calculated and injected in real-time with a feedback manner based on the power supply voltage measurement with the impedance characteristics of ATE's original power delivery network (PDN) and the customer PDN. Experimental results of prototype circuits are demonstrated to show that the compensation current emulates the impedance, and the both power supply voltage fluctuation waveforms agree well.

Biography

Naoki Terao is currently a graduate student at the Department of Electrical Engineering and Information Systems, the University of Tokyo. He received a B.S. degree from the University of Tokyo in 2016. He belongs to D2T research division and is working on a research project for ATE technology in collaboration with ADVANTEST corporation. He is a recipient of Chairman's Award for his graduation thesis submitted to the University of Tokyo in 2016, which was also presented at ITC2016.

Hosted by:
Dr. Krishnendu Chakrabarty